The present invention is generally directed to the field of semiconductor manufacturing, and, more particularly, to various methods for forming conductive through-wafer vias and for forming stacked packages.
Integrated circuit technology relies on transistors to formulate vast arrays of functional circuits. The complexity of these circuits requires the use of an ever-increasing number of linked transistors. As the number of transistors increases, the integrated circuitry dimensions shrink. One challenge in the semiconductor industry is to develop improved methods for electrically connecting and packaging circuit devices which are fabricated on the same and on different integrated circuit dies or chips. In general, it is desirable in the semiconductor industry to construct circuits which occupy less surface area on the silicon chip/die.
As integrated circuit technology progresses, there is a growing desire for a “system on a chip.” Ideally, a computing system would be fabricated with all the necessary integrated circuits on one wafer, as compared with today's method of fabricating many chips of different functions and packaging them to assemble a complete system. Such a structure would greatly improve integrated circuit performance and provide higher bandwidth. In practice, it is very difficult with today's technology to implement a high-performance “system on a chip” because of vastly different fabrication processes and different manufacturing yields for the various logic and memory circuits.
As a result, there are economic advantages associated with forming a module or system from an interconnected group of different types of previously-tested integrated circuits. One way of connecting circuit elements at the interface of a module or integrated circuit is to form an electrically conductive via or passage through a wafer or die.
For these applications, a metal filled void-free through via is desired. The conventional fill process is to plate metal into the via. To achieve a complete void-free via, bottom up plating is a typical approach. However, such bottom up plating is difficult. First, due to the high aspect ratio of the via, the diffusion of metal ions from a plating solution to the bottom of the via results in a slow fill rate. Second, plating thickness is not uniform with the layer near the bottom of the via being much thinner than the layer at the opening of the via. The application of a higher plating current density only exacerbates the problem as the significantly higher deposit rate at the via opening results in metal filling the upper portion of the via before the bottom of the via can be filled. Plating chemistry has been modified in an attempt to accomplish a void-free via. These attempts include additives to suppress plating at the opening of the via and additives to accelerate the diffusion of ions into the via. A suitable plating chemistry has not been identified. The application of a low current density for current (DC) plating or pulse and reverse-pulse plating techniques have been used to completely fill a via. Unfortunately, these process techniques are time consuming taking from hours for relatively small volume vias to days for larger vias.
Consequently, successful and efficient methods of forming conductive void free through-wafer vias are desired.